1. Field of the Invention
The present invention relates to a parallel analog-to-digital converter (ADC) preferably used in image-display processors that require high-speed conversion. More specifically, the invention relates to a parallel ADC that can greatly reduce the number of comparators required.
2. Prior Art
A conventional, high-speed, n-bit parallel ADC is configured as shown in FIG. 1. In FIG. 1, numeral 2 designates a reference-voltage-generating circuit having a plurality of resistors connected serially. Four resistors 4, one at the far left, one at the far right, and two at the center are of R/2 .OMEGA., and the other resistors 6 are of R .OMEGA.. To end terminals Ta and Tb of reference-voltage-generating circuit 2 are applied positive reference voltage V.sub.RH and negative reference voltage V.sub.RL, respectively (these reference voltages are called fundamental reference voltages in contrast to individual reference voltages mentioned below). In addition, to center terminal Tc is applied center voltage V.sub.RM which has a voltage between the positive reference voltage V.sub.RH and the negative reference voltage V.sub.RL, e.g., 0 volt.
The voltage between terminals Ta and Tb of reference-voltage-generating circuit 2 is equally divided into 2.sup.n levels by resistors 4 and 6. Consequently, individual-reference-voltage nodes P1 to Pk (k=2.sup.n -1) presents individual reference voltages V1 to Vk. Any two consecutive voltages of these nodes are of a constant difference. Each of these reference voltages Vl to Vk is applied to one input of each of the comparators C1 to Ck, respectively. To the other input of each comparator thereof, analog input voltage V.sub.in to be converted is simultaneously applied through input terminal T.sub.in, respectively. Hence, each comparator simultaneously compares analog input voltage V.sub.in with individual reference voltages Vl to Vk, and supplies the result of the comparisons to encoder 8. Encoder 8 converts the k-bit comparator outputs into an n-bit binary code. Thus, analog input voltage V.sub.in applied to input terminal T.sub.in is converted into n-bit digital data at a very high speed, and the digital data is produced from output terminal T.sub.out.
The conventional n-bit parallel ADC described above, however, necessitates 2.sup.n -1 (=k; the same number as that of individual reference voltages V1 to Vk) comparators because the reference voltages V1 to Vk are generated by equally dividing the voltage between positive reference voltage V.sub.RH and negative reference voltage V.sub.RL into 2.sup.n. For this reason, a great number of high-precision comparators are required for an increasing number of bits of digital output data. In addition, the larger the number of bits, the more complex encoder 8 must be. These factors hinder the production of low-cost, high-density integrated circuits of the ADC.